1. Field of the Invention
The present invention relates to a gate circuit for bus signal lines used upon a LSI (Large Scale Integration) device. More particularly, the present invention relates to a gate circuit having a failure detecting circuit for making the choice of bus signal lines when a processing unit controls the gates of the gate elements.
2. Description of the Prior Art
FIG. 5 shows a gate circuit for bus signal lines with a tri-status bus circuit which has been broadly used upon a LSI device of a conventional microcontroller.
In the drawing, a gate circuit for bus signal lines includes the tri-status gates as gate elements 1-3, bus signal lines 1a-3a, gate signal lines 1b-3b, functional block of a microcontroller F0-F5 showing Micro Read Only Memory F0, Data Path F1, Interrupt Controller F2, Timer F3, Random Access Memory F4, and Universal Asynchronous Receiver Transmitter F5 respectively, inner bus IBUS which mutually connects with F0-F5, and control circuits G1-G3.
Referring to FIG. 5, the gate circuit for bus signal lines includes three tri-status gates.
These tri-status bus circuits supply the control signals C1-C3 to the gates of the said tri-status gates through the gate signal lines 1b-3b for making the choice of input signals provided through bus signal lines 1a-3a and control each of the states of the tri-status bus gates 1-3.
Then, for example, in the case that the control signals, C1-C3, are switched to the "1" state, the tri-status gates 1-3 turn to the "ON" state control micro code signal MIC, output from micro ROM F0, is designed not to provide two control signals at the same time and also not to turn a plurality of the tri-status gates 1-3 to the "ON" state. FIG. 6 shows an example of a PLA circuit consisting of control circuits G1-G3 as shown in FIG. 5. These circuits decode micro code signal MIC from micro ROM F0 and thereby output control signals C1-C3.
The above mentioned tri-status bus circuit does not include any detecting circuit for each of the tri-status gates 1-3. Any failure occurring in control circuits G1-G3 etc. provide error control signals C1-C3 to gate signal lines 1b-3c. Even when a plurality of tri-status gates 1-3 have turned to the "ON" state simultaneously, any failure that has not been detected, causes the problem that the reliability of data to be output to inner bus IBUS is decreased.